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| SL74HC651 Octal 3-State Bus Transceivers and D Flip-Flops High-Performance Silicon-Gate CMOS The SL74HC651 is identical in pinout to the LS/ALS651. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. These devices consists of bus transceiver circuits, D-type flip-flop, and control circuitry arranged for multiplex transmission of data directly from the data bus or from the internal storage registers. Direction and Output Enable are provided to select the read-time or stored data function. Data on the A or B Data bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock pins (A-to-B Clock or B-to-A Clock) regardless of the select or enable or enable control pins. When A-to-B Source and B-toA Source are in the real-time transfer mode, it is als o possible to store data without using the internal D-type flip-flops by simulta-neously enabling Direction and Output Enable. In this configuration each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state. The SL74HC651 has inverted outputs. * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 2.0 to 6.0 V * Low Input Current: 1.0 A * High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC651N Plastic SL74HC651D SOIC TA = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM PIN 24=VCC PIN 12 = GND SLS System Logic Semiconductor SL74HC651 MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 35 75 750 500 -65 to +150 260 Unit V V V mA mA mA mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figures 2,3) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus. SLS System Logic Semiconductor SL74HC651 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 C to -55C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 0.5 85 C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 5.0 125 C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.0 10 A A V Unit VIH Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage VOUT=0.1 V or VCC-0.1 V IOUT 20 A VOUT=0.1 V or VCC-0.1 V IOUT 20 A VIN=VIH or VIL IOUT 20 A VIN=VIH or VIL IOUT 6.0 mA IOUT 7.8 mA 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 V VIL V VOH V VOL Maximum Low-Level Output Voltage VIN= VIL or VIH IOUT 20 A VIN=VIH or VIL IOUT 6.0 mA IOUT 7.8 mA) IIN IOZ Maximum Input Leakage Current Maximum Three-State Leakage Current VIN=VCC or GND (Pins 1,2,3,21,22,and 23) Output in High-Impedance State VIN= VIL or VIH VOUT=VCC or GND, I/O Pins VIN=VCC or GND IOUT=0A ICC Maximum Quiescent Supply Current (per Package) 6.0 8.0 80 160 A SLS System Logic Semiconductor SL74HC651 AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input t r=t f=6.0 ns) VCC Symbol tPLH, t PHL Parameter Maximum Propagation Delay, Input A to Output B (or Input B to Output A) (Figures 2,3 and 9) Maximum Propagation Delay, A-to-B Clock to Output B (or B-to-A Clock to Output A) (Figures 1 and 9) Maximum Propagation Delay, A-to-B Source to Output B (or B-to-A Source to Output A) (Figures 4 and 9) Maximum Propagation Delay , Direction or Output Enable to Output A or B (Figures 5,6 and 10) Maximum Propagation Delay , Direction or Output Enable to Output A or B (Figures 5,6 and 10) Maximum Output Transition Time, Any Output (Figure 2) Maximum Input Capacitance Maximum Three-State I/O Capacitance (Output in High-Impedance State Power Dissipation Capacitance (Per Channel) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 C to -55C 180 36 31 240 48 41 220 44 37 170 34 29 180 36 31 60 12 10 10 15 85C 225 45 38 300 60 51 275 55 47 215 43 37 225 45 38 75 15 13 10 15 125C 270 54 46 360 72 61 330 66 56 255 51 43 270 54 46 90 18 15 10 15 Unit ns tPLH, t PHL ns tPLH, t PHL ns tPLZ, t PHZ ns tPZL, t PZH ns tTLH, t THL ns CIN COUT pF pF Typical @25C,VCC=5.0 V 60 pF SLS System Logic Semiconductor SL74HC651 TIMING REQUIREMENTS(Input t r=t f=6.0 ns) VCC Symbol tsu Parameter Minimum Setup Time, Input A to A-to-B Clock (or Input B to B-to-A Clock) (Figure 7) Minimum Hold Time, A-to-B Clock to Input A (or B-to-A Clock to Input B) (Figure 7) Minimum Pulse Width, A-to-B Clock (or B-to-A Clock) (Figure 7) Maximum Input Rise and Fall Times (Figures 2 and 3) V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 C to-55C 50 10 9 25 5 5 75 15 13 1000 500 400 85C 65 13 11 30 6 5 95 19 16 1000 500 400 125C 75 15 13 40 8 7 110 22 19 1000 500 400 Unit ns th ns tw ns tr, t f ns TIMING DIAGRAM SLS System Logic Semiconductor SL74HC651 FUNCTION TABLE Dir. L OE H CAB CBA SAB SBA X X X X X X A INPUTS Z INPUTS B INPUTS Z INPUTS FUNCTION Both the A bus and the B bus are inputs. The output functions of the A and B bus are disabled. Both the A and B bus are used for inputs to the internal flip-flops. Data at the bus will be stored on low to high transition of the clock inputs. The A bus are outputs and the B bus are inputs. The data at the B bus are displayed at the A bus. The data at the B bus are displayed at the A bus. The data of the B bus are stored to the internal flip-flops on low to high transition of the clock pulse. The data stored to the internal flip-flops, are displayed at the A bus. The data at the B bus are stored to the internal flip-flops on low to high transition of the clock pulse. The states of the internal flip-flops output directly to the A bus. OUTPUTS X* L L X* X X X L L H L H L INPUTS L H L H X* X* X X X H H Qn L H X H L INPUTS X H H X* X* L L X X H L H L OUTPUTS The A bus are inputs and the B bus are outputs. L H L H The data at the A bus are displayed at the B bus. The data at the B bus are displayed at the A bus. The data of the B bus are stored to the internal flip-flops on low to high transition of the clock pulse. The data stored to the internal flip-flops are displayed at the B bus. The data at the A bus are stored to the internal flip-flops on low to high transition of the clock pulse. The states of the internal flip-flops output directly to the B bus. The data stored to the internal flip-flops are displayed at the A and B bus respectively. The output at the A bus are displayed at the B bus, the output at the B bus are displayed at the A bus respec. X X* X* H H X X X H L Qn L H OUTPUTS H L X X H H Qn OUTPUTS Both the A bus and the B bus are outputs Qn H H Qn Qn X : DON'T CARE Z : HIGH IMPEDANCE Qn : THE DATA STORED TO THE INTERNAL FLIP-FLOPS BY MOST RECENT LOW TO HIGH TRANSITION OF THE CLOCK INPUTS * : THE DATA AT THE A AND B BUS WILL BE STORED TO THE INTERNAL FLIP-FLOPS ON EVERY LOW TO TRANSITION OF THE CLOCK INPUTS SLS System Logic Semiconductor SL74HC651 SWITCHING DIAGRAMS Figure 1. Switching Waveforms Figure 2. A Data Port = Input, B Data Port = Output Figure 3. A Data Port = Output, B Data Port = Input Figure 4. Switching Waveforms Figure 5. Switching Waveforms SLS System Logic Semiconductor SL74HC651 Figure 6. Switching Waveforms Figure 7. Switching Waveforms Figure 9. Test Circuit Figure 10. Test Circuit SLS System Logic Semiconductor SL74HC651 EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor |
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